CoE-CPPICS offers comprehensive assembly and packaging solutions tailored specifically for photonic integrated circuits (PICs). Whether you require assistance with chip prototypes, our dedicated packaging team is committed to optimizing your design from the outset.

Photonic packaging is pivotal in integrating essential elements, such as a fiber-chip coupling, photonic integrated circuits (PICs), and photodetectors. Notably, two robust vertical grating-coupling schemes, the V-Groove Array (VGA) and Quasi-Planar Coupling (QPC), are widely recognized for their exceptional optical alignment tolerances in fiber-chip coupling methods. To ensure a stable configuration of the PIC, we adopt an effective approach by placing the Thermo-Electric Cooler (TEC) and thermistor beneath it to facilitate efficient heat dissipation. Our power management involves using a programmable power supply with a printed circuit board (PCB) to drive essential components like the LASER, PICs, TEC, and thermistors. The interconnection between PICs and the PCB is achieved through precise wire bonding. With a specialized focus on VGA/QPC coupling in PICs and proficiency in efficient electrical packaging, including driver circuitry and wire bonding, we collaborated with iZMO Microsystems, Bengaluru, India. Together, we developed both the electrical and optical packaging phases.

The principles governing photonic packaging encompass various factors such as chip dimensions, grating coupler spacing, channel count, and clearance for fibers. Additionally, the electrical connections are delineated by the pitch and dimensions of DC and RF bond pads, which are typically specified in the layout of the photonic integrated circuit (PIC) on the left side of the diagram.

For further query related to layout design rules and services, kindly contact our CTO Arnab Goswami [Email id:] cto-cppics[at]