Photonic IC (PIC) packaging requires both electrical as well as optical interfacing. Current packaging strategies include monolithic co-integration, flip-chip bonding, and hybrid integrations. However, no standard packaging rules have been recognized so far for universal usages. Recently, there have been demands for multifunctional Field Programmable Photonic Gate Array (FPPGA) alongside presently available Application Specific PIC (ASPIC) design modules. CoE-CPPICS has committed to developing indigenous PIC design rules and hardware infrastructure for precision packaging in in-house system-level applications and field trials. In this mission, CoE-CPPICS IIT Madras has signed an MoU with Si2 Microsystems, Bangalore (https://www.si2microsystems.com/) for joint development of packaging rules, transfer of technology and futuristic start-up business.