• SOI Technology
• SiN Technology
• Si-SiN Hybrid Technology

Silicon On Insulator (SOI) technology, initially developed for improving electronic chip transistors, holds great promise for advancing silicon photonic wire waveguides. The high index contrast of the Si-SiO2 system allows for strong light confinement and tight waveguide bends (~5 µm), enabling the creation of compact and low-loss photonic devices. The maturation of SOI-based CMOS technology has fast-tracked the progress of silicon photonics over the past two decades. The SOI platform shows potential for large-scale integration in various applications like microwave photonics, quantum information processing, lab-on-chip sensing, artificial intelligence, and neuromorphic computing. Starting in 2007 at the Integrated Optoelectronic Laboratory, IIT Madras, we established a world-class silicon photonics research facility.

Our journey began with a waveguide demonstration on the 5 µm thick SOI platform. Over time, we scaled our technology to sub-micron and nanoscale dimensions, adhering to industry standards. With an in-house fabrication facility at the Centre for NEMS and Nanophotonics (CNNP), IIT Madras, we developed diverse passive and active photonic devices, showcasing both novelty and state-of-the-art capabilities. As the Centre for Photonics and Photonic Integrated Circuits (CPPICS), our goal is to scale our technology for extensive integration of photonic devices and circuits, focusing on applications in Microwave and Quantum photonics. Leveraging our expertise, we aim to contribute significantly to advanced technologies in these domains.

Silicon nitride waveguide technology (SiN) is gaining major attention due to its relatively lower waveguide losses, wider most important aspects for the realization of large-scale photonic integrated circuits with acceptable waveguide losses and fabrication yields. We are able to grow good quality thermal oxide wafers transparency and less sensitivity to temperature fluctuations and fabrication variations. The growth of an optical grade oxide layer (for bottom cladding) and subsequent deposition of SiN device layer are the (~2 µm) and stoichiometric, crack-free SiN wafers (~0.4 µm) with excellent wafer scale variations.

We have also been able to demonstrate losses below 1 dB/cm and 3 dB/cm in LPCVD (Low Pressure Chemical Vapour Deposition) and PECVD (Plasma Enhanced Chemical Vapour Deposition) SiN platforms (both on 2 µm thermal oxide) respectively using traditional waveguide technolgy like the SOI process which involves patterning on device layer. Both the platforms were developed completely indigenously here at CPPICS, IITM starting only with 4 inch bare Si wafer.

The silicon-on-insulator (SOI) and Silicon Nitride (SiN) platforms have been extremely successful in PIC development due to their CMOS compatibility. The devices are usually fabricated on a wafer following a planar process, where only one core material with a defined thickness is included. This traditional single-material platform cannot provide all the functionalities required for fully integrated PICs. By embedding thin-film SiN onto the SOI platform, SiN/Si hybrid photonic devices can be integrated on the same chip, simultaneously leveraging the advantages of both material platforms.

Advanced PICs may require the best possible performance of a large number of different photonic elements in PICs to achieve the desired functionalities, which may not be possible with single waveguide material technology. In-plane SiN/Si hybrid integrated photonic devices can offer clear advantages over single platform-based devices. First benefit is that we can get high-speed modulators and photo-detector arrays, with the feasibility of fabricating these devices in Silicon-on-Insulator (SOI) which is the most widely accepted platform for high speed active modulation. Secondly,for passive components like routing waveguides and delay lines, SiN material offers lower loss.