We are delighted to share that two of our recent research works have been presented by our research scholars at the 7th International Conference on Emerging Electronics IEEE ICEE 2025 in Bengaluru, India. These works reflect our continued efforts toward compact modeling and seamless co-integration of electronics and photonics on silicon platforms.
Compact Modeling of Lateral-Gate Transistors for Co-Integrated Electronics in Si-Photonic Platforms
This work demonstrates low-cost co-integration of EICs and PICs within a silicon photonics fabrication flow. We present the design of lateral-gate transistors and the development of SPICE Level-3, Verilog-A based compact models. Using these models, we successfully demonstrate key CMOS circuits such as inverters, 2-input NAND and NOR gates, MUX, and DeMUX, enabling EPDA simulations, early-stage circuit analysis, co-simulation, and process-variation studies.
We congratulate Kumar Piyush for leading this work and presenting it at ICEE 2025. We also acknowledge the valuable contributions of the co-authors Kamaraja Siddhartha Chaganti, Manu Maxim, Dr Shamsul Hassan, Arnab Goswami, and our faculty mentors Prof. Deleep Nair, Prof. Bijoy Krishna Das, and Prof. Anjan Chakravorty from IIT Madras, for their constant guidance. Special thanks to Yusman Mohd Yusof and Chew Yan Ng from our foundry partner SilTerra Malaysia Sdn. Bhd. for their critical feedback and support.
Compact Modeling of Ge-on-Si Waveguide Photodetector Operating in the Optical C-Band
Photodetectors are a key building block of any PIC. In this work, we develop a compact model capturing current saturation effects, along with both DC and AC response, enabling fast and accurate SPICE-level co-simulation of electronic and photonic devices. This effort is part of our broader initiative to build compact models for fundamental PIC building blocks, essential for scalable electronic photonic co-design and photonic system level simulation in Spice.
We congratulate ANJANA JAMES for leading this work and presenting it at ICEE 2025, and acknowledge the contributions of Pawan Kumar, Arnab Goswami, and Dr Shamsul Hassan, along with the continuous guidance from Prof. Deleep Nair, Prof. Bijoy Krishna Das, and Prof. Anjan Chakravorty.
We sincerely thank our foundry partner SilTerra Malaysia Sdn. Bhd. for their tremendous support in device fabrication, without which this work would not have been possible.
We look forward to continued discussions, collaborations, and advancing the field of CMOS-compatible electronic photonic co-integration.
